arm: socfpga: Move cache_enable to CPU code

Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.

Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Acked-by: Pavel Machek <[email protected]>

diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index 76186c511b5c20670253ee21c2d91284ea38e55d..7f9d7f01337d219310a049d9e5e925aa7dcbc5b5 100644 (file)
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -33,6 +33,16 @@ int dram_init(void)
        return 0;
 }
 
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+       icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+       dcache_enable();
+#endif
+}
+
 /*
  * DesignWare Ethernet initialization
  */

diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index 6b982778be0780146a5cebc6f5137a4579d2dc65..0f81d899a6cf873f37b952bedfb79130752084a9 100644 (file)
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -34,9 +34,6 @@ int board_early_init_f(void)
  */
 int board_init(void)
 {
-       icache_enable();
-       dcache_enable();
-
        /* Address of boot parameters for ATAG (if ATAG is used) */
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;